1) Field of the Invention
The present invention relates to semiconductor devices and methods for fabricating the same.
2) Description of Related Art
In recent years, rapid miniaturization in the field of semiconductor devices has spurred the trends toward higher-speed operation and lower power consumption. Accordingly, the need for improvement in transistor performance becomes imperative. However, improvement in performance only by miniaturization will soon hit a ceiling. To cope with this, various novel techniques, such as a technique in which stress is applied to the channel region of a MIS transistor, have been developed to enhance the performance of a MIS transistor.
FIG. 26 is a cross-sectional view illustrating the configuration of MIS transistors on which stress-applying films are formed according to a known art. In the configuration illustrated in FIG. 26, an N-channel MIS transistor 201 is covered with a LP-CVD (low-pressure chemical vapor deposition) film 203 generating tensile stress, and a P-channel MIS transistor 202 is covered with a plasma CVD film 204 generating compressive stress, thereby enhancing the performance of each MIS transistor (see, for example, Japanese Unexamined Patent Publication No. 2003-273240).
FIG. 27 is a plan view illustrating the configuration of transistors forming an SRAM according to a known art. As illustrated in FIG. 27, in the known SRAM, an active region 303 of an access transistor TrA has a narrower width (channel width) than an active region 304 of a drive transistor TrD. For this structure, when the drive transistor TrD has a higher performance than the access transistor TrA, this can suppress malfunction of the SRAM.
However, the above-mentioned method in which the active region 303 of the access transistor TrA has a different width from the active region 304 of the drive transistor TrD places limitations on the layout of transistors. When deviations from the proper locations of transistors are caused, for example, due to a lithography process in fabrication of transistors, the gate length and channel width of each transistor cannot be adjusted to desired values. This has the opposite effect of allowing the transistor characteristics to significantly vary. When a large fabrication margin is provided to prevent the above-mentioned opposite effect, this prevents the size of cells from being miniaturized.
The above-mentioned problems are caused not only in transistors forming SRAMs but also in any transistor formed on a wafer as long as the performance of transistors needs to be adjusted.